Encapsulated arrays with barrier layer covered tiles
US8960262B2 · kind B2 · utility
2Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/239
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
Encapsulated arrays with tiles covered with a barrier layer are disclosed. Tiles formed of silicon carbide, and wrapped with a barrier layer, are encapsulated with a base metal formed of a steel alloy. During a casting process, to fabricate the encapsulated arrays, the barrier layer prevents the steel alloy and/or the silicon carbide from compromising each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.