Multiple well drain engineering for HV MOS devices
US8962397B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Jul 20, 2012 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jun 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.