Method for manufacturing fan-out lines on array substrate

US8962404B2 · kind B2 · utility

Assignees

• BOE Technology Group Co., Ltd. · CN
• BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. · CN

Inventors

• Jinchao Bai · Beijing, CN
• Liang Sun · Beijing, CN
• Xiangqian Ding · Beijing, CN
• Liangliang Li · Beijing, CN
• Yao Liu · Baoshan, TW

Key dates

• Filing date: Nov 12, 2013
• Grant date: Feb 24, 2015
• Expiry date: Nov 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/60

Abstract

A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; forming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.