Enhancement-mode HFET circuit arrangement having high power and a high threshold voltage
US8963209B2 · kind B2 · utility
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6References
18Claims
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Key dates
| Filing date | Feb 4, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.