Power semiconductor device and fabrication method thereof
US8963260B2 · kind B2 · utility
9Cited by
1References
12Claims
0Family size
Assignee
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Key dates
| Filing date | May 26, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.