Stacked chip package and method for forming the same
US8963312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2014 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jul 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.