Heterogeneous chip integration with low loss interconnection through adaptive patterning
US8963313B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2011 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.