Power stage
US8963586B2 · kind B2 · utility
1Cited by
43References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2014 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.