Clock generation using fixed dividers and multiplex circuits
US8963587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | May 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.