Patent · US Active

Multi-phase clock signal generation circuits

US8963605B2 · kind B2 · utility

0Cited by

2References

12Claims

0Family size

Assignee

INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

Weiwei Chen · Beijing, CN
Lan Chen · Beijing, CN
Shuang Bo Long · Keelung, TW

Key dates

Filing date	Nov 30, 2011
Grant date	Feb 24, 2015
Priority date	—
Expiry date	Jun 12, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1508
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.