On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure
US8963657B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jan 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.