Circuit for digitizing a sum of signals
US8963754B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 10, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Sep 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/452
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.