Adaptive frequency synthesis for a serial data interface
US8964922B2 · kind B2 · utility
0Cited by
3References
5Claims
0Family size
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Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.