On-chip memory (OCM) physical bank parallelism
US8966152B2 · kind B2 · utility
28Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Jan 26, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.