State machine for monitoring a trace port and verifying proper execution of a secure mode entry sequence instruction
US8966226B2 · kind B2 · utility
5Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.