Decoder supporting multiple code rates and code lengths for data storage systems
US8966339B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Feb 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of decoders supporting multiple code rates and code lengths for data storage systems are disclosed. The decoders can provide for flexible and scalable decoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. The decoder can be scaled in size based on, for example, the desired decoding throughput and/or computational cycle duration. In one embodiment, a rotate-left/right shifter is configured to support data having processing units of one of multiple matrix sizes and independently shift portions of the data. In another embodiment, one or more decoding modules are configured to share with one or more other decoding modules an output value from a layer decoding operation. This sharing can facilitate parallel decoding of data by the decoding modules. As a result, decoding speed, efficiency, and system performance can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.