Clock tree generation and routing
US8966425B1 · kind B1 · utility
28Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.