CMOS imaging device with three-dimensional architecture having reading circuits and an electronic processing circuit arranged on different substrates
US8969773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Dec 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging device including: plural pixels each including a photodetector; plural reading circuits associated with the plural photodetectors, each reading circuit including a first MOS transistor charging/discharging a photodetector and a second MOS transistor converting charges to be output by the photodetector into voltage; an electronic processing circuit configured to process the voltages outputted by the reading circuits; a first substrate on which are formed the pixels and the reading circuits, and a second substrate, distinct from the first substrate, on which is formed the electronic processing circuit, the second substrate being linked electrically to the first substrate by an electrical interconnection forming an electrical link between the reading circuits and the electronic processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.