Conversion circuitry for reducing pixel array readout time
US8969774B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Nov 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register (“SAR”) analog-to-digital-converter (“ADC”), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array (“FCA”) that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array (“SCA”) that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.