CMOS circuit for sensor with reduced read noise
US8969780B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 15, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/813
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A CMOS image sensor having one or more pixels, e.g. in an array, whereby each of the pixels having two or more sub-pixel elements for generating charge according to incident light intensity as well as a common charge sensitive device such as an amplifier coupled to two or more sub-pixel elements of a respective pixel. Charges generated by the two or more sub-pixel elements are added and integrated over respective integration time periods, to provide a signal representing the integrated charges. The circuit can be configured so that the two or more sub-pixel elements have different integration time periods. By combining charges at the charge sensitive device rather than combining outputs of multiple such devices, the amount of read noise can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.