Memory device
US8969843B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Aug 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.