Stacked packages having through hole vias
US8970025B2 · kind B2 · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2014 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | May 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.