Phase offset cancellation circuit and associated clock generator
US8970273B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Nov 27, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Nov 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase offset cancellation circuit and associated clock generator, include a first modifying phase interpolator and a second modifying phase interpolator, and provide a first modified clock and a second modified clock according to a first to a fourth input clocks; wherein the first and the third clocks are of opposite phases. The first modifying phase interpolator performs equal phase interpolation between the first and the second input clocks to generate the first modified clock, and the second modifying phase interpolator performs equal phase interpolation between the third and the fourth input clocks to generate the second modified clock, such that a phase difference between the first modified clock and the second modified clock is of substantially 90 degrees, against phase offsets between the first to the fourth input clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.