Latch-based array with enhanced read enable fault testing
US8971098B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Sep 10, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Sep 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.