Method of measuring threshold voltage of MOS transistor in SRAM array
US8971099B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 30, 2014 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Mar 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of measuring threshold voltages of MOS transistors in a SRAM array are provided. The SRAM array includes array-arranged cells having a first pass NMOS transistor, a second pass NMOS transistor, a first pull-down NMOS transistor, a second pull-down NMOS transistor, a first pull-up PMOS transistor, and a second pull-up transistor. A cell is selected from the SRAM array by a row decoding and a column decoding. A voltage is applied to a word line, a first bit line, a second bit line, a first power line, a second power line, a first substrate terminal, and/or a second substrate terminal, that are connected to the selected cell. A bit line current of the selected cell is measured to obtain a threshold voltage of a MOS transistor in the selected cell. Threshold voltages of a large number of MOS transistors in a SRAM array can be measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.