Patent · US Active

Semiconductor device periodically updating delay locked loop circuit

US8971143B2 · kind B2 · utility

0Cited by
3References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 8, 2011
Grant dateMar 3, 2015
Priority date
Expiry dateJul 25, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C11/40615
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.