Dual-port SRAM with bit line clamping
US8971146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Aug 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory includes a plurality of bit lines and a write driver for driving a driven bit line selected from the plurality of bit lines during a write operation. The write driver is coupled to an internal node. A first stage clamping circuit is operable to clamp the internal node to a clamping voltage if the write operation is not enabled and is further operable to unclamp the internal node during the write operation. The memory further includes a multiplexer for selectively coupling the driven bit line to the internal node. A second stage clamping circuit is operable to clamp the plurality of bit lines to a clamping voltage if the write operation is not enabled and is further operable to unclamp the driven bit line during the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.