System and method for accelerating and decelerating packets
US8971321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Oct 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2011/0086
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system for accelerating a packet stream includes a first accelerator configured to re-clock the packet stream from a first clock rate to a second clock rate to produce an accelerated packet stream, where the first clock rate is less than the second clock rate, where the packet stream has a first inter-packet gap, where the accelerated packet stream has a second inter-packet gap, and where the second inter-packet gap is greater than the first inter-packet gap. The system also includes a switch coupled to the first accelerator, where the switch is configured to switch the accelerated packet stream at the second clock rate to produce a switched packet stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.