Windowed-based decision feedback equalizer and decision feedback sequence estimator
US8971396B1 · kind B1 · utility
7Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for performing Decision Feedback Equalization (DFE) and Decision Feedback Sequence Estimation (DFSE) in high-throughput applications that are not latency critical. In an embodiment, overlapping blocks of samples are used to allow for the parallelization of the computation and the breaking of the critical path. In addition, the overlap of the windows addresses issues associated with performance loss due to what is termed “ramp-up” and “ramp-down” BER loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.