Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof
US8971718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Mar 8, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.