Vector conflict instructions
US8972698B2 · kind B2 · utility
12Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.