Adaptive error correction codes for data storage systems
US8972826B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.