System and method for functional verification of multi-die 3D ICs
US8972918B2 · kind B2 · utility
0Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Feb 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318513
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.