Multistage development workflow for generating a custom instruction set reconfigurable processor
US8972958B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Oct 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and systems which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions. A framework generator and hardware description language complier are also included in the multistage workflow of embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.