Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8972995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2010 |
| Grant date | Mar 3, 2015 |
| Priority date | — |
| Expiry date | Jan 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.