MOS transistor, formation method thereof, and SRAM memory cell circuit

US8975703B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International Corp. · CN

Inventors

• Zhenghao Gan · Shanghai, CN
• Junhong Feng · Shanghai, CN

Key dates

• Filing date: Jan 11, 2013
• Grant date: Mar 10, 2015
• Expiry date: Mar 16, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory.