Package structure and method for manufacturing thereof
US8975739B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2014 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.