Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method
US8975938B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | May 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.