System for a clock shifter circuit
US8975942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2012 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Mar 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.