Level shift circuit utilizing resistance in semiconductor substrate
US8975944B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2011 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Oct 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.