Offset reduction for analog front-ends
US8975963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | May 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45526
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based on the output signal, where the offset sensor includes a second amplifier configured to generate an offset reduction signal for the first amplifier based on the sensed DC offset. A T-network in the circuit includes at least three resistors coupled to provide a feedback connection between the input signal and the output signal for the first amplifier and to receive the offset reduction signal to mitigate DC offset in the first amplifier. Since this method reduces the low-frequency component of the signal, it also shapes and reduces the flicker noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.