BEMF monitor gain calibration stage in hard disk drive servo integrated circuit
US8975964B2 · kind B2 · utility
0Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Feb 5, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.