Method and apparatus for Vernier ring time to digital converter with self-delay ratio calibration
US8976053B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Oct 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.