SRAM performance monitor
US8976575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Aug 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit can include an array of static random access memory (SRAM) cells. A first SRAM cell may provide a first current through an insulated gate field effect transistor (IGFET) having a first conductivity type. A second SRAM cell may provide a second current through an IGFET having a second conductivity type. A first current division slew circuit can provide a first slew output current proportional to the first current to change the charge on a first slew capacitor. A second current division slew circuit can provide a second slew output current proportional to the second current to change the charge on a second slew capacitor. A pulse may be generated having a first edge determined by a launch signal and a second edge determined by the time the first or the second capacitor reach a predetermined potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.