Semiconductor integrated circuit device
US8976608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.