Power and area efficient receiver equalization architecture with relaxed DFE timing constraint
US8976855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03471
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.