Method and apparatus for preventing multiple threads of a processor from accessing, in parallel, predetermined sections of source code

US8977795B1 · kind B1 · utility

Assignee

• Marvell International Ltd. · BM

Inventors

• Olaf Mater · Blankenloch, DE
• Sascha Schmeckenbecher · Karlsruhe, DE

Key dates

• Filing date: Oct 23, 2012
• Grant date: Mar 10, 2015
• Expiry date: May 30, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2209/522
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Systems, methods, and other embodiments associated with managing access to critical sections in a multithread processor are described. According to one embodiment, an apparatus includes a register configured to store i) respective resource identifiers that identify respective resources and ii) respective priorities for respective resource identifiers. The apparatus includes a managing module logic configured to receive a blocking instruction for a first resource having a first resource identifier that is associated with a first task, access the register to determine a priority associated with the first resource identifier, select one or more dependent resources based, at least in part on the priority associated with first resource identifier, and block the first resource and the dependent resources. In this manner the first task is granted access to the first resource and the dependent resources while other tasks are prevented from accessing the first resource and the dependent resources.