Architecture for cooperating hierarchical microcoded compute engines
US8977838B1 · kind B1 · utility
3Cited by
4References
2Claims
0Family size
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Key dates
| Filing date | Oct 1, 2010 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | Jun 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nested hierarchical plurality of microcoded compute engines where each successive compute engine is coupled to a source bus and a sink bus of another microcoded computed engine at a different hierarchical level, where one microcoded compute engine may be a replacement of a scratchpad memory or FIFO from a pre-existing design. A communication scheme for communicating between and within various hierarchical layers of microcoded compute engines and a piano roll of bitmapped barrier objects for synchronizing activities of various microcomputer engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.