Programmable logic device data rate booster for digital signal processing
US8977885B1 · kind B1 · utility
2Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2012 |
| Grant date | Mar 10, 2015 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.