Method of fabricating chip scale package
US8980697B2 · kind B2 · utility
3Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.